1. Field of the Invention
The present invention relates to a reset circuit used in an electronic device and, more particularly, to a reset circuit for a processor such as a CPU (Central Processing Unit) and an MPU (Micro Processing Unit).
2. Description of the Related Art
A reset operation is denoted such that, for example, the Q outputs from all flip-flops such as registers and counters are set to a level "0" (i.e., "L"). In an arithmetic and logic processor such as a CPU and an MPU, the system is preferably set in a predetermined state upon a power ON operation, and therefore power-ON reset which uses a rise in a power supply voltage as a signal is often used.
Alternatively, by use of an external reset switch, the system is set again in the same state as that obtained after a power ON operation, or otherwise the arithmetic and logic processor is initialized.
For this reason, normally the above arithmetic and logic processor has a reset terminal or a clear terminal for initializing internal circuits. When a reset signal is supplied to the reset terminal, the internal circuits such as flip-flops are initialized.
Conventionally, for an arithmetic and logic processor (simply referred to as a processor hereinafter) such as a CPU and an MPU, there is provided:
1. a reset circuit for forcibly supplying a reset signal to the reset terminal of the processor, or
2. a reset circuit for supplying a reset signal to the reset terminal of the processor as an interrupt process when software processing is temporarily interrupted on the basis of software processing conditions and the like in the processor.
More specifically, in the above case 1, a reset signal (more specifically, a reset pulse) is generated in accordance with a reset signal request which is externally input. The reset signal generated is then output to the reset terminal of the processor, thereby initializing the internal units of the processor.
In the above case 2, the arithmetic processor is normally executing various processes based on predetermined programs. When the program processing is being executed, predetermined status information is output during a normal operation. Thus, if the program execution processing causes a runaway due to any reason and no more status information is output, it is determined that an abnormality has occurred in the program execution processing. At this time, a reset signal is output to the reset terminal of the processor as an interrupt signal, thereby performing initialization of the processor.
However, in a reset scheme stated in the above case 1, if a reset signal request is issued during an access to a memory such as a built-in RAM (Random Access Memory) by the processor, a reset signal is output to the reset terminal of the processor. For this reason, the following problem is occurs.
More specifically, in such a memory access state, information stored in the memory is being changed by a rewriting operation or the like, and the contents of the memory are not defined yet. Therefore, when the processor is reset in such an unstable state, there is the possibility that the contents of the memory are destroyed.
This is based on the same reason, for example, as that for inhibiting an eject operation during an access to a floppy disk (FD) in a floppy disk drive (FDD). If the process is resumed with the contents of the memory destroyed, an unexpected failure may occur.
In a reset scheme stated in the above case 2, when the program execution processing causes a runaway due to any reason and no more status information is output, it is determined that an abnormality has occurred in the program execution processing, and a reset signal is output to the reset terminal of the processor as an interrupt signal. For this reason, the following problem occurs.
More specifically, if a wait terminal or a bus hold terminal etc. are also locked due to the runaway of the processor, the status information is fixed as it is though the processor is in the runaway state. Therefore, the processor cannot be reset permanently.